1. Field of the Invention
This invention relates to a memory data copying apparatus which is interposed between a pair of systems each including a central processing unit (CPU) and a main storage apparatus and is constructed to multiplex data read out from the main storage apparatus of one of the two systems with corresponding address information and successively write and read the thus multiplexed data and address information into and from a FIFO (first-in first-out) memory to copy the data into the main storage apparatus of the other system.
2. Description of the Related Art
Various memory data copying apparatus of the type mentioned are already known, and an exemplary one of such conventional memory data copying apparatus is shown in FIG. 5. Referring to FIG. 5, the copying apparatus includes an address.data multiplexing circuit 610, an error detection circuit 620, a FIFO memory 640, and an address.data demultiplexing circuit 631. The copying apparatus multiplexes, by means of a multiplexing section 650 of the address.data multiplexing circuit 610 thereof, address information and data transmitted thereto from the main storage apparatus of a first system not shown and writes the multiplexed data and address information into the FIFO memory 640 under the control of a write control section 660. In this instance, one of the following methods is used.
In particular, in the first method, it is detected by the error detection circuit 620 whether or not an error is involved in accessing to the main storage apparatus of the first system, and after presence or absence of an error is determined, the FIFO memory 640 is accessed so that, when absence of an error is determined, the address information and the data are written into the FIFO memory 640, but when presence of an error is determined, none of the address information and the data is written into the FIFO memory 640.
In the second method, the address information and the data are written once into the FIFO memory 640 irrespective of presence or absence of an error, and thereupon, if a result of detection by the error detection circuit 620 proves presence of an error, error information is added. Then, upon reading out from the FIFO memory 640, such error information is checked, and if absence of an error is determined, then the address information and the data read out from the FIFO memory 640 are demultiplexed by the address.data demultiplexing circuit 631 and copied into the main storage apparatus of the second system, but on the contrary if presence of an error is determined, then the data and the address information read out are abandoned.
With the first method, however, since the FIFO memory is accessed without fail after error detection processing is performed by the error detection circuit to check presence or absence of an error and besides, when presence of an error is determined, the FIFO memory is accessed although none of the address information and the data is to be written into the FIFO memory, a waiting time is produced before a writing operation into the FIFO memory, which reduces the processing rate of the copying apparatus, resulting in deterioration of the processing capacity of the entire system. Further, when an error occurs, since address information is not available at the destination of copying, there is a problem since processing is complicated there is trouble with the system.
On the other hand, with the second method, since address information and data are written into the FIFO memory irrespective of presence or absence of an error, when an error occurs frequently when the main storage apparatus is accessed successively, the amount of wrong and unnecessary data written in the FIFO memory increases, which deteriorates effective use of the FIFO memory. Consequently, not only the processing capacity of the FIFO memory is deteriorates, but also the FIFO memory may possibly overflow.